Field
Embodiments of the present invention generally relate to techniques for temperature-compensated offset cancellation for high-speed amplifier circuits.
Description of the Related Art
Within an amplifier, input offset voltage is a parameter defining a differential direct current (DC) voltage required between the inputs of the amplifier to make the output voltage zero. However, the input offset voltage value tends to drift with temperature or other conditions.
For amplifiers used within high-speed applications such as serial display links, the input offset voltage can cause a degradation of the output duty cycle (called “duty-cycle distortion” or DCD). DCD can cause display data to be missed or misinterpreted, which directly degrades display performance (e.g., displaying jittery images, incorrect pixels, etc.). One technique for mitigating DCD includes screening the silicon during the manufacturing process, and discarding dies that exhibit unacceptably large offsets. However, this technique tends to reduce yield and increase production costs.
Another technique for mitigating DCD includes adding offset cancellation circuitry to the amplifiers. However, conventional offset cancellation circuitry may exhibit a temperature dependence. Further, offset cancellation circuitry that includes switching elements and/or capacitors can introduce distortion and jitter if the switching events do not occur at a frequency much greater than the amplifier's bandwidth. Naturally, the added distortion and/or jitter may degrade the amplifier's high-frequency performance.